Course Project: Pipelined Analog to Digital Converter Design

Project Description and Report Guidelines: (download pdf)

Ideal Pipelined ADC Model and Testbenches: (download)

• Current library revision : Rev01, uploaded on 12/09
  
  Many ideal blocks in the library are modeled using Verilog-A, an analog behavioral description language. The language reference document for Spectre simulator can be found at following location on EWS machines.

/software/Cadence/MMSIM111/doc/veriaref/veriaref.pdf

To run longer simulations on EWS machines, it is necessary to increase CPU time limit for processes. Following sequence of commands in the terminal can be used to increase CPU time limit to 36000 sec for simulations:

bash
ulimit -t 36000
ece581
virtuoso

Extra Credit Problems: (download)

Sample MATLAB Simulation Files

IMPORTANT: The following MATLAB and Simulink files work with MATLAB R2013a. The Simulink model does not work with MATLAB R2011a. To load MATLAB R2013a on EWS workstation, use the following module command in terminal before starting MATLAB:

module load matlab/R2013a

• Main MATLAB script for simulation : pipeline_1p5bit_sim.m

• Simulink model for simulation : pipeline_1p5bit_sim.slx

• MATLAB function for spectrum plot : plot_spectrum.m (Updated 10/18)

• MATLAB function for DNL calculation : find_dnl.m