General Information

Instructor

Deming Chen (dchen AT illinois.edu)

Office Hours: CSL 410, Tuesday 4:00-5:00PM or appointments by email (Put ECE527 on the subject line)

http://www.ece.illinois.edu/directory/profile.asp?dchen

Teaching Assistant

-Ashutosh Dhar (adhar2 AT illinois.edu)

--Office Hours: CSL423 Wednesday, 2PM-4PM

-Sitao Huang (shuang91 AT illinois.edu)

--Office Hours: CSL421 Monday, 3PM-5PM

Credits

4 hours

Lectures

2013 Electrical and Computer Engineering Bldg

11-12:20pm, Tuesday and Thursday

Lab

4022 Electrical and Computer Engineering Bldg

Allocated time slots: 8PM-12AM for Monday-Friday, and Weekends

Prerequisites

ECE 425 (or equivalent), ECE 391 (or equivalent)

Piazza Homepage

Link

General Description

System-on-a-chip

(SOC) is an idea of integrating all components of a computer system into a single chip. SOC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. Gartner regards them as the most important type of semiconductor device since the development of the microprocessor. An important enabler for the design of SOCs is the availability of semiconductor intellectual property (IP), which allows a SOC designer to include predefined circuitries, cutting development cycle while increasing product functionality, performance and quality. The implementation of these systems of both hardware and software components and the interaction between hardware and software is an essential part of the design. This course will cover SOC topics on design process, modeling and analysis, design methodology and platform, hardware/software co-design, behavioral synthesis, embedded software, verification, and design space exploration. With a focus on learning of the current SOC design and research topics, students are given opportunities to carry out class projects based on their own interest. Class projects can include software/hardware partitioning, hardware implementation of video compression algorithms, and synthesis for application specific instruction set processors (ASIP). Platform FPGA boards and digital cameras are provided to students to prototype, test, and evaluate their SOC designs.

Textbooks

Supplementary Materials

Grading Policy

Machine problem 1: 5% (70% actual work + 30% report)

Machine problem 2: 7% (70% actual work + 30% report)

Machine problem 3: 5% (70% actual work + 30% report)

Machine problem 4: 10% (70% actual work + 30% report)

All machine problems are to be done in a 2-person team


Class participation: 5%

Homework: 10%

Midterm: 20%

Research Project 38%: (70% actual work + 20% report + 10% presentation)

Lateness Policy

15% off/day, cannot be more than 3 days late.

For late homework, please deliver to Professors office (leave in the folder at the door) and send an email for the time stamp. For machine problems you can email it to the TA.