ECE 498NS/598NS: Deep Learning in Hardware
Course Description
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Description: This course will present challenges in implementing deep learning algorithms on resource-constrained hardware platforms at the Edge such as wearables, IoTs, autonomous vehicles, and biomedical devices. Fixed-point requirements of deep for deep neural networks and convolutional neural networks including the back-prop based training will be studied. Algorithm-to-architecture mapping techniques will be explored to trade-off energy-latency-accuracy in deep learning digital accelerators and analog in-memory architectures. Fundamentals of learning behavior, fixed-point analysis, architectural energy and delay models will be introduced in just-in-time manner throughout the course. Case studies of hardware (architecture and circuit) realizations of deep learning systems will be presented. Homeworks will include a mix of analysis and programming exercises in Python and Verilog leading up to a term project.
Syllabus: ECE 498NSU/598NSG syllabus
Prerequisite: ECE 342 and ECE 313 or equivalent. Students should be familiar with programming in Python. HDL (Verilog) programming experience is desirable.
Time and Place: 11:00am-12:20pm, TuTh, 3015 ECE Building
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Instructor
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Professor Naresh Shanbhag
Department of Electrical and Computer Engineering
Web page: http://shanbhag.ece.illinois.edu
Office Hours: Mondays 3PM to 4PM in CSL 414
Email: shanbhag AT illinois DOT edu
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Teaching Assistants
Charbel Sakr
Hassan Dbouk
Annoucements
2019/8/27: Welcome to ECE 498NSU/598NSG!
2019/9/5: Homework-1 has been assigned and is due on 2019/9/19
2019/9/19: Homework-2 has been assigned and is due on 2019/10/4
2019/9/21: Homework-1 solution is online
2019/10/1: Lecture on Tuesday October 8 is cancelled - a make up lecture will be arranged
2019/10/4: Homework-3 has been assigned and is due on 2019/10/29
2019/10/29: Homework-4 has been assigned and is due on
2019/11/12: The course project has been assigned
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