ECE 462: Logic Synthesis
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
Final Exam: Thursday, December 15, 2016, 7:00pm-10:00pm. Openbook and notes. Laptops, notebooks, e-pads, and cell phones allowed.
Final Exam Template
Instructor: Professor Janak H. Patel
Office: 250 CSL
Office Hours: 1:30pm to 3:30pm Tuesdays in Room 250 CSL
Teaching Assistant: Dongbo Wang
Office Hours: 4:00pm to 6:00pm Wednesdays in Room 3036 ECEB
Lectures: 11am-12:20pm Tuesdays and Thursdays, Room 2017 ECEB
Prerequisites: Introduction to Logic Design
This course teaches fundamentals of Logic Design, Verification and Testing. The topics covered include synthesis of two-level logic, synthesis of incompletely specified combinational logic, multi-level logic synthesis, binary decision diagrams, finite state machine synthesis, automatic test pattern generation and design for test, equivalence checking and reachability analysis of finite machines, and technology mapping.
1. Logic Synthesis and Verification Algorithms, by Hachtel and Somenzi, Springer Science (on reserve in Library)
2. Logic Design Principles, by E. J. McCluskey (on reserve in Library).
3. Finite State Models for Logical Machines by F. C. Hennie, Publisher: John Wiley & Sons (on reserve in Library)
4. Switching and Finite Automata Theory, by Z. Kohavi Publisher: McGraw Hill (on reserve in Library)
Homework (20 percent)
Two Mideterm Exams (20 percent each)
Final Exam (40 percent)