Labs

Overview

Each lab has several checkpoints in it. You are required to demo the checkpoints to your TA during each lab session. Many labs build upon past work (if you construct an I2C serial interface in one lab, you will probably need to use it later on), so you are strongly encouraged to understand each assignment.

Assignments

Lab

Assigned Date (week of)

Due Date (week of)

Primary Reference Documents Additional Reference Documents
Lab 1 1/24 1/31
Lab 2 1/31 2/7
Lab 3 2/7 2/14
Lab 4 2/14 2/21
Lab 5 2/21 2/28
Lab 6 2/28 3/7  
Midterm Exam 3/7 3/28
Spring Break 3/14      
Lab 7 3/28 4/4  
Lab 8 4/4 4/11
  • CMOSIS imager datasheet
  •  
    Lab 9 4/11 4/18
  • BTPipeExample.v
  • ClockGenerator.v
  • BTPipeOut_Example.py
  • CMOSIS imager datasheet
  • Block Throttled Pipe Out module
  • ReadFromBlockPipeOut Python function
  • Lab 10 4/18 4/25    
    Final Project 4/25      

     

    Here are some additional resources that will help you with your lab assignments:

    Links Document Description
    Front Panel API Front Panel online API
    Front Panel HDL Front Panel online HDL documentation
    Verilog online reference Excellent online reference for Verilog
    Python tutorial Online reference for Python