Reference Material

Lab Material (Fall 2017)

 

Xilinx/Verilog Files

  • You can install Vivado WebPACK for free on your computer.

  • Sending data from FPGA to PC with WireOuts.

      Description: Here is an example code in both Verilog and Python demonstrating how to send data from the FPGA to the PC using WireOuts. The project file can he retrieved here.

      Two constant values are transferred from the FPGA to the PC. The zip file contains the entire Verilog project and you should be able to open the project in Vivado. All support files from Front Panel are inserted in the right directory and the project will correctly synthetize.

      In the top directory of the project, you will find a python file that allows you to program the *.bit file, receive data from the FPGA and print the results on the screen. The python file name is: comm_example_edit.py. Run this file under your typical Python IDE.

Python

Opal Kelly