Date
|
Topic
|
Reading
|
01/15/2019 |
Introduction |
Weste & Harris: 1.1, 1.5.1, 1.6 |
01/17/2019 |
IC Fabrication |
Weste & Harris: 1.3, 1.5.1-2 |
01/22/2019 |
Circuits and Layout, Circuits and Layout-full equations |
Weste & Harris: 1.4, 1.5.3-5 |
01/24/2019 |
MIPS Case Study |
Weste & Harris: 1.7-1.12 |
01/29/2019 |
CMOS Transistor Theory (1), CMOS Transistor Theory (1)-full equations |
Weste & Harris: 2.1-2.4 |
01/31/2019 |
CMOS Transistor Theory (2), CMOS Transistor Theory (2)-full equations |
Weste & Harris: 2.5, 4.1-4.3 |
02/01/2019 |
(MP0 Report Due) |
02/05/2019 |
SPICE, MP1 Introduction |
Weste & Harris: 8.1, 8.2 |
02/07/2019 |
Combinational Circuit Design , Combinational Circuit Design-full equations (HW1 Due) |
Weste & Harris: 4.4.1-4.4.4; 4.5.1; 9.1-9.2.2 |
02/12/2019 |
Sequential Circuit Design , Sequential Circuit Design-full equations |
Weste & Harris: 10.1-10.3.4 |
02/14/2019 |
Wires , Wires-full equations |
Weste & Harris: 6.1-6.2.2; 6.3.1-6.3.3; 6.4.1-6.4.2 |
02/19/2019 |
Adders, Adders-full equations |
Weste & Harris: 11.1-11.2.2.8 |
02/21/2019 |
Multipliers and Other FUs, Multipliers and Other FUs-full equations |
Weste & Harris: 11.3-4; 11.8-9 |
02/26/2019 |
(MP1 Report Due) |
02/26/2019 |
SRAMs, MP2 Introduction |
Weste & Harris: 12.1-12.2.5 and 12.5 |
02/28/2019 |
CAMs, ROMs, PLAs, CAMs, ROMs, PLAs-full equations |
Weste & Harris: 12.4-12.7 |
03/05/2019 |
Modeling Digital Systems, Verilog (HW2 Due) |
Weste & Harris: Appendix A |
03/07/2019 |
Midterm Overview |
03/12/2019 |
Midterm,Midterm Solution |
03/14/2019 |
Circuit Pitfalls and Design for Test , Circuit Pitfalls and Design for Test-full equations |
Weste & Harris: 7.1-7.3; 15.1-15.7 |
04/02/2019 |
Design for Low Power , Design for Low Power-full equations |
Weste & Harris: 5.1-5.3 |
04/04/2019 |
VLSI Design Styles |
Weste & Harris: 14.3 |
03/29/2019 |
(MP2 Checkpoint Report Due) |
04/09/2019 |
VLSI CAD Tools |
Weste & Harris: 14.4 |
04/11/2019 |
High-Level Synthesis (1) |
G. De Micheli: 5 |
04/11/2019 |
High-Level Synthesis (2) |
G. De Micheli: 6 |
04/16/2019 |
Logic Synthesis (1) |
G. De Micheli: 2.5-2.5.1 |
04/16/2019 |
Logic Synthesis (2) |
G. De Micheli: 2.5.2 |
04/18/2019 |
Partitioning and Floorplan, MP3 Introduction |
N. Sherwani: 5.1-5.4, 6.1 |
04/19/2019 |
(MP2 Report Due) |
04/23/2019 |
Placement and Routing |
N. Sherwani: 7-7.1, 7.4, 8-8.4, 9.1.3, 9.4.2 |
04/25/2019 |
Final Exam Overview (HW3 Due) |
04/30/2019 |
Final Exam |
05/03/2019 |
(MP3 Report Due, Hard Deadline) |