ECE 425 - Introduction to VLSI System Design

Lectures


Date

Topic

Reading
08/29/2017 Introduction Weste & Harris: 1.1, 1.5.1, 1.6
08/31/2017 IC Fabrication Weste & Harris: 1.3, 1.5.1-2
09/05/2017 Circuits and Layout, Circuits and Layout-full equations Weste & Harris: 1.4, 1.5.3-5
09/07/2017 MIPS Case Study Weste & Harris: 1.7-1.12
09/12/2017 CMOS Transistor Theory (1), CMOS Transistor Theory (1)-full equations Weste & Harris: 2.1-2.4
09/14/2017 CMOS Transistor Theory (2), CMOS Transistor Theory (2)-full equations Weste & Harris: 2.5, 4.1-4.3
09/15/2016 (MP0 Report Due)
09/19/2017 SPICE, MP1 Introduction Weste & Harris: 8.1, 8.2
09/21/2017 Combinational Circuit Design, Combinational Circuit Design-full equations (HW1 Due) Weste & Harris: 4.4.1-4.4.4; 4.5.1; 9.1-9.2.2
09/26/2017 Sequential Circuit Design, Sequential Circuit Design-full equations Weste & Harris: 10.1-10.3.4
09/28/2017 Wires, Wires-full equations Weste & Harris: 6.1-6.2.2; 6.3.1-6.3.3; 6.4.1-6.4.2
10/03/2017 Adders, Adders-full equations Weste & Harris: 11.1-11.2.2.8
10/05/2017 Multipliers and Other FUs, Multipliers and Other FUs-full equations Weste & Harris: 11.3-4; 11.8-9
10/06/2017 (MP1 Report Due)
10/10/2017 SRAMs, MP2 Introduction Weste & Harris: 12.1-12.2.5 and 12.5
10/12/2017 CAMs, ROMs, PLAs, CAMs, ROMs, PLAs-full equations Weste & Harris: 12.4-12.7
10/17/2017 Modeling Digital Systems, Verilog (HW2 Due) Weste & Harris: Appendix A
10/19/2017 Midterm Overview
10/24/2017 Midterm
10/26/2017 Circuit Pitfalls and Design for Test, Circuit Pitfalls and Design for Test-full equations Weste & Harris: 7.1-7.3; 15.1-15.7
10/31/2017 Design for Low Power, Design for Low Power-full equations Weste & Harris: 5.1-5.3
11/02/2017 VLSI Design Styles Weste & Harris: 14.3
11/03/2017 (MP2 Checkpoint Report Due)
11/07/2017 VLSI CAD Tools Weste & Harris: 14.4
11/09/2017 High-Level Synthesis (1) G. De Micheli: 5
11/14/2017 High-Level Synthesis (2) G. De Micheli: 6
11/16/2017 Logic Synthesis (1) G. De Micheli: 2.5-2.5.1
11/21/2017 (Thanksgiving Break)
11/23/2017 (Thanksgiving Break)
11/28/2017 Logic Synthesis (2), MP3 Introduction G. De Micheli: 2.5.2
11/30/2017 Partitioning and Floorplan N. Sherwani: 5.1-5.4, 6.1
11/30/2017 (MP2 Report Due)
12/05/2017 Placement and Routing (HW3 Due) N. Sherwani: 7-7.1, 7.4, 8-8.4, 9.1.3, 9.4.2
12/07/2017 Final Exam Overview
12/12/2017 Final Exam
12/15/2017 (MP3 Report Due, Hard Deadline)