| Date | Topic | Homework Schedule | Reading |
| 1 | 08/27/18 | KCL, KVL, Thevenin and Norton Theorems | | Notes/Subtitution Theorem/notes-SP-2018 |
| 2 | 08/29/18 | Two-port networks | | Notes/notes-SP-2018 |
| 3 | 08/31/18 | Large & Small-signal models - General concept | HW 1 assigned | Notes/4.2-4.3/notes-SP-2018 |
| 09/03/18 | Labor Day | | |
| 4 | 09/05/18 | Diode device structure, large-signal model & DC analysis | | Notes/4.2-4.3/notes-SP-2018 |
| 5 | 09/07/18 | Diode small-signal models and analysis | HW 1 due. HW 2 assigned | Notes/4.2-4.3/notes-SP-2018 |
| 6 | 09/10/18 | MOS technology & terminal I-V behavior | | Notes/5.1-5.3/Updated 02/12/18:notes-SP-2018 |
| 7 | 09/12/18 | DC analysis of circuits with MOSFETs | | Notes/5.1-5.3/notes-SP-2018 |
| 8 | 09/14/18 | DC analysis, continued | HW 2 due. HW 3 assigned. | Notes/5.1-5.3 |
| 9 | 09/17/18 | Small-signal model of MOSFET | | Notes/7.1-7.3/notes-SP-2018 /notes-SP-2018 |
| 10 | 09/19/18 | CS amplifier - DC behavior | | Notes/7.1-7.3/notes-SP-2018 |
| 11 | 09/21/18 | AC (linear) model of CS amp | HW 3 due. HW 4 assigned. | Notes/7.3.3,7.5.1 |
| 12 | 09/24/18 | Voltage gain of CS amp (continued from previous class) | | Notes/7.3.3,7.5.1 |
| 13 | 09/26/18 | Terminal impedances of MOSFETs (low-freq.). Input and output resistance of CS amp. | | Notes |
| 14 | 09/28/18 | Using Gm, Rin and Rout to find gain of CS amp (“alternative method”)/Alternate Gain Calculation Method Examples | HW 4 due. HW 5 assigned. | Notes/notes-SP-2018 |
| 15 | 10/01/18 | Analysis of CS amp with source degeneration | | Notes/7.3.5-6/notes-SP-2018 |
| 16 | 10/03/18 | Analysis of CG amplifier | | Notes/7.3.5-6/notes-SP-2018 |
| 17 | 10/05/18 | Analysis of CD amplifier | HW 5 due. | Notes/7.3.5-6/notes-SP-2018 |
| 18 | 10/08/18 | BJT regions of operation. I-V equations for forward active region. | | Notes/6.1-6.2 |
| 10/10/18 | MIDTERM 1 (7-8 PM) | | |
| 19 | 10/12/18 | DC analysis of circuits with BJTs. | HW 6 assigned. | Notes/6.3 |
| 20 | 10/15/18 | BJT small-signal model. Voltage gain of CE stage. | | Notes/7.2.2 |
| 21 | 10/17/18 | BJT terminal impedances | | Notes |
| 22 | 10/19/18 | Emitter degenerated CE amp (Av, Rin, Rout) | HW 6 due. HW 7 assigned. | Notes/7.3.4/notes-Fall-2018 |
| 23 | 10/22/18 | CB and CC amps | | Notes/notes-Fall-2018 |
| 24 | 10/24/18 | Frequency response. Transfer functions. | | Notes/Appendix F/notes-Fall-2018 |
| 25 | 10/26/18 | Complex numbers. Bode plots. | HW 7 due. HW 8 assigned. | Notes/Appendix F/notes-Fall-2018 |
| 26 | 10/29/18 | Transistor intrinsic capacitances. | | Notes |
| 27 | 10/31/18 | Procedure to derive the approximate transfer function directly from the circuit schematic. Miller's Theorem. Open circuit time constants. | | Notes/notes-SP-2018/notes-SP-2018/notes-Fall-2018 |
| 28 | 11/02/18 | Frequency response of CE and CS amps | HW 8 due. HW 9 assigned. | Notes |
| 29 | 11/05/18 | Frequency response of CB/CG amps. Frequency response of cascaded CS/CE amps. | | Notes |
| 30 | 11/07/18 | Introduction to feedback. Properties of negative feedback. | | Notes/notes-SP-2018 |
| 31 | 11/09/18 | Previous topic, continued. Brief introduction to positive feedback. | HW 9 due. | |
| 32 | 11/12/18 | Stability of systems with negative feedback. | | Notes/notes-SP-2018 |
| 11/14/18 | MIDTERM 2 (7-8 PM) | | |
| 33 | 11/16/18 | Stability of systems with negative feedback | | |
| Thanksgiving Break(11/17/2018 - 11/25/2018) | | | |
| 34 | 11/26/18 | Previous topic, continued (includes loop gain and phase margin). | HW 10 assigned. | Notes/notes-SP-2018 |
| 35 | 11/28/18 | Examples: feedback and stability analysis | | Notes/notes-SP-2018 |
| 36 | 11/30/18 | Introduction to CMOS logic. RC delay model for CMOS inverter. | | Notes/14.1,14.5/notes-SP-2018 |
| 37 | 12/03/18 | Transistor sizing | HW 10 due. HW 11 assigned. | Notes/14.1,14.5/notes-SP-2018 |
| 38 | 12/05/18 | PDN and PUN design for complementary static logic gates | | Notes/14.1,14.5/notes-SP-2018 |
| 39 | 12/07/18 | Transistor sizing in combinational logic gates | | Notes/14.1,14.5/notes-SP-2018 /notes-SP-2018 |
| 40 | 12/10/18 | Transistor sizing in combinational logic gates | HW 11 due. | Notes/14.1,14.5/notes-SP-2018 /notes-SP-2018 |
| 41 | 12/12/18 | Review | | |
| 12/15/18 | Final Exam (7-10 PM) | |
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