Spring 2018

ECE 110

Course Notes

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Metal-oxide-semiconductor field effect transistors (MOSFETs) are the fundamental building blocks of digital electronics. Since the 1970s, electrical engineers have been able to reduce the size of MOSFETs from micrometers to tens of nanometers. Over the same period of time, the number of MOSFETs contained in a state-of-the-art microprocessor has increased at an exponential rate from thousands to billions.

Figure 1

Fig. 1: An array of microprocessors fabricated on a wafer of silicon crystal. A typical wafer has a diameter of 300 mm (12 inches) and a thickness of less than 1 mm. Image source.

MOSFETs are made by a process called planar fabrication that involves several stages of oxide growth and etching, heated diffusion of chemical impurities, and deposition and etching of metal layers upon the semiconductor wafer. In the diffusion stages, the semiconductor is doped to create wells of p-type and n-type semiconductor. MOSFETs are fabricated in two complementary varieties, called PMOS and NMOS, which differ in their configurations of p-type and n-type wells. In ECE 444: Theory and Fabrication of Integrated Circuits, students fabricate MOSFETs and other electronic devices in a clean room facility.

Figure 2

Fig. 2: Cross-section of NMOS and PMOS field effect transistors. Each MOSFET has 4 terminals called body (B), source (S), gate (G) and drain (D). Note that the gate terminal is electrically insulated from the semiconductor by a layer of oxide (shown in gray). Image source.

The gate terminal of a MOSFET is typically considered its input. Since the gate is separated from the semiconductor body by an insulating oxide layer, the gate-body connection exhibits many properties of a capacitor. One property is that no current flows into the gate terminal on average. Another capacitative property is that the gate and body terminals can support an electric field between them. This electric field can attract mobile charges towards either the gate or body terminals and repel them from the other. By changing the charge distribution between gate and body, the MOSFET's drain-source (or source-drain) connection can be opened or connected. In this way, NMOS and PMOS transistors operate as a switches, but the details of the mechanism differ between the two varieties.

An NMOS transistor is usually wired with the body and source connected together to ground and the drain terminal connected to a fixed voltage $V_{DD}$ (often $5 \text{ V}$). We consider two values of the gate terminal voltage $V_G$, namely ground and $V_{DD}$, to illustrate the operating principle.

Figure 3

Fig. 3: NMOS transistor with open drain-source connection. When $V_G = 0 \text{ V}$ (ground), there is no voltage drop between gate and body, so there is no electric field across the gate-body connection. In this state, no current can flow from the drain to the source because of the deficit of electrons in the p-type substrate that separates the n-type wells.

Figure 4

Fig. 4: NMOS transistor with connected drain-source connection. When $V_G = 5 \text{ V}$ ($V_{DD}$), the voltage drop from gate to body creates an electric field, which draws sparse electrons from the p-type substrate and concentrates them near the oxide layer. This charge redistribution induces a continuous n-type channel between the n-type wells and allows current to flow from drain to source.

A PMOS transistor is typically configured in a way complementary to an NMOS transistor. The body and source are connected together to $V_{DD}$, while the drain is connected to ground. The role of the gate voltage $V_G$ is also reversed with respect to the NMOS case.

Figure 5

Fig. 5: PMOS transistor with open source-drain connection. When $V_G = 5 \text{ V}$ ($V_{DD}$), there is no voltage drop between gate and body, so there is no electric field across the gate-body connection. In this state, no current can flow from the source to the drain because of the deficit of positively charged holes in the large n-type well that separates the embedded p-type wells.

Figure 6

Fig. 6: PMOS transistor with connected source-drain connection. When $V_G = 0 \text{ V}$ (ground), the voltage drop from body to gate creates an electric field, which draws sparse (positively charged) holes from the large n-type well and concentrates them near the oxide layer. This charge redistribution induces a continuous p-type channel between the embedded p-type wells and allows current to flow from source to drain.

Fig. 3 to Fig. 6 illustrate the operation of MOSFETs in specific cases only. We can describe their behavior more completely by plotting their I-V characteristics. In this section, we present an NMOS transistor model that takes advantage of the fact that its body and source terminals are usually both wired to ground as in Fig. 3 and Fig. 4. For the same reason, most symbols for an NMOS show just three terminals: gate, drain and source.

Figure 7

Fig. 7: The circuit symbol for an NMOS transistor. The input voltage $V_{GS}$ drops from gate to source. (Note that $V_{GS}=V_G$ in Fig. 3 and Fig. 4 since the body and source terminals are grounded in those diagrams.) On the output side, $I_D$ flows into the drain and $V_{DS}$ drops from drain to source. Notice that the NMOS transistor symbol incorporates the symbol for a capacitor to signify the gate's capacitative properties.

If the input $V_{GS}$ is fixed, an output I-V characteristic can be traced relating $I_D$ to $V_{DS}$. Varying $V_{GS}$ therefore produces a family of curves. We model the operation of an NMOS transistor by dividing the I-V space into 3 modes, OFF, ACTIVE and OHMIC, and fitting linear equations to each I-V curve in each mode.

Figure 8

Fig. 8: Approximate linear model for output I-V characteristic. The mode boundaries depend on a constant threshold voltage $V_{TH}$, which can be found on a datasheet. If $V_{GS} < V_{TH}$, the NMOS is OFF and $I_D=0$ (just like in Fig. 3). But if $V_{GS} > V_{TH}$ and $V_{DS} > V_{GS}-V_{TH}$, then the NMOS is ACTIVE and $I_D=k(V_{GS}-V_{TH})^2$, which is fixed with respect to $V_{DS}$. The parameter $k$ (also found on a datasheet) has dimensions $\text{A}/\text{V}^2$. Otherwise, if $V_{GS} > V_{TH}$ and $V_{DS} < V_{GS}-V_{TH}$, the NMOS is said to be OHMIC and $I_D$ is increasing in $V_{DS}$; a very rough linear approximation is $I_D=k(V_{GS}-V_{TH})V_{DS}$. The modes and their conditions and behavior are summarized in Table 1.

Conditions Mode Behavior under Linear Model
\begin{aligned} V_{GS}& < V_{TH}\end{aligned} OFF \begin{aligned} I_D=0 \end{aligned}
\begin{aligned} V_{GS}& > V_{TH} \\ V_{DS}& > V_{GS}-V_{TH}\end{aligned} ACTIVE \begin{aligned} I_D=k(V_{GS}-V_{TH})^2 \end{aligned}
\begin{aligned} V_{GS}& > V_{TH} \\ V_{DS}& < V_{GS}-V_{TH}\end{aligned} OHMIC \begin{aligned} I_D=k(V_{GS}-V_{TH})V_{DS} \end{aligned}

Figure 9

Fig. 9: NMOS transistor connected a Thévenin subcircuit. You can apply the load line method to analyze an NMOS transistor connected to a Thévenin subcircuit, consisting of $V_{DD}$ and $R_D$. Intersect the NMOS output I-V characteristic in Fig. 8 with the Thévenin subcircuit's I-V characteristic to find the operating point $(V_{DS},I_D)$ and the mode which it represents.

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