Spring 2018
A Diode Problem with Unterminated LEads
Learn It!
Pre-Requisite Knowledge
Solve the for \(V_{out}\) assuming the large signal model for the diode
If \(V_{in}=1.7 V\) in the diode circuit below, what is \(V_{out}\), assuming the large signal model for the diode \(V_{on}=0.7 V\)

\[ \begin{align} &a.& 0 V \\ &b.& 0.7 V\\ &c.& 1 V\\ &d.& 1.7 V\\ &e.& 2.4 V\\ \end{align} \]
What should we do about those terminals?
Part 1
Guess diode mode
The first thing to do when a diode is connected to a DC source is guess if it will be on or off.

Since the \(+\) end of the source is connected to the back of the diode, and the source is larger than 0.7V, we'll take "on" as our 1st guess
Compute values using KVL
\[ +V_{in} - V_{on} -V_{out}=0 \]
Apply KVL. The source is positive, the voltage drop across the diode and resistor are both negative.
\[ V_{out}=1.7-0.7=1.0 V\]
Just plug it in to solve.
What about what's attached to the terminals?