﻿ Logic Circuits and CMOS
Spring 2019

ECE 110

Course Notes

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Digital logic is the mathematical manipulation of zeroes and ones. (Other names for the logical values $0$ and $1$ are: low and high; false and true; and off and on.) Virtually all computing today is performed by digital logic circuits built out of MOSFETs. But MOSFETs (like other electronic devices) operate on voltages and currents, which are analog quantities. We bridge the gap between analog and digital by interpreting ranges of voltages as logical values.

Figure 1

Fig. 1: Mapping from voltages to logical values. Voltages between ground and a certain threshold represent the logical value $0$. Voltages between a higher threshold and $V_{DD}$ represent the logical value $1$. The threshold levels are design choices. If a voltage falls in the gap between the defined logical ranges, the result is undefined and there must be an error in the logic circuit that produced it.

A benefit of mapping a whole range of voltages to a single logical value is that it allows us to make aggressive approximations in circuit analysis. For example, in order to see whether a logical value is $1$, we do not need check that the corresponding voltage is exactly $V_{DD}$, just that it is approximately $V_{DD}$. Extending this reasoning leads to a useful set of logic circuit approximations for NMOS and PMOS transistors.

MOSFET
Type
Logic Circuit
Symbol
$A=0$
Approximation
$A=1$
Approximation
NMOS
PMOS
Table 1: MOSFET logic circuit symbols and approximations.

The logic circuit symbol for an NMOS transistor (shown above in Table 1) is slightly different to its analog circuit symbol. In a logic circuit, an NMOS transistor is always drawn with the drain terminal at the top and the source terminal at the bottom. In contrast, the logic circuit symbol for a PMOS transistor is always drawn with the source terminal at the top and the drain terminal at the bottom. The PMOS transistor symbol includes a bubble at the gate terminal that represents logical inversion (to be explained below). Note also that the input $A$ labeled at the gate terminal of each MOSFET in Table 1 is a logical value. When $A=0$, the voltage at the gate terminal is close to ground; when $A=1$, the gate terminal voltage is close to $V_{DD}$.

The approximations in Table 1 replace each MOSFET's drain-source connection with an open or short circuit depending on the type of MOSFET (NMOS or PMOS) and the logical value $A$. These substitutions are justified by the way that a MOSFET's gate-body connection behaves like a capacitor controlling its drain-source connection. To give a specific example, an NMOS transistor with $A=0$ has gate voltage close to ground, and consequently its drain-source connection is open. When $A=1$, the NMOS transistor's gate voltage is close to $V_{DD}$, and so it has a connected drain-source connection. The corresponding PMOS transistor substitutions are reversed with respect to the value of $A$. Abstractly, you can imagine that the PMOS transistor first inverts $A$ (from $0$ to $1$, or from $1$ to $0$) and then behaves the same way as an NMOS transistor. This imaginary logical inversion is represented by the bubble in the PMOS transistor's logic circuit symbol.

Complementary metal-oxide-semiconductor (CMOS) technology encompasses a design method and a set of processes for building reliable and power-efficient digital logic circuits out of NMOS and PMOS transistors. A CMOS circuit is reliable because its design guarantees that its output is always shorted to either ground or $V_{DD}$ but not both at the same time. As a consequence, the design also ensures that $V_{DD}$ is never shorted to ground through $Z$, which makes CMOS circuits power-efficient. We now use several examples to illustrate how the NMOS and PMOS transistors are arranged to provide these guarantees.

Figure 2

Fig. 2: One-input logic circuit. This circuit (called a CMOS inverter or a NOT logic circuit) takes as input a logical input $A$ and outputs the opposite logical value $Z$. Note that the PMOS transistor connects $V_{DD}$ to $Z$ and the NMOS transistor connects $Z$ to ground. We validate that this circuit inverts the value of $A$ by checking each input case (i.e. $A=0$ and $A=1$) separately in Table 2.

$A$ Logic Circuit
with Substitutions
$Z$ Explanation
$0$
$1$ When $A=0$, the NMOS and PMOS drain-source connections are approximated as an open and a short circuit, respectively, as in Table 1. In this way, $Z$ is shorted directly to $V_{DD}$ and isolated from ground. Therefore, $Z=1$.
$1$
$0$ When $A=1$, the NMOS and PMOS drain-source connections are approximated as a short and an open circuit, respectively, as in Table 1. In this way, $Z$ is shorted directly to ground and isolated from $V_{DD}$. Therefore, $Z=0$.

Figure 3

Fig. 3: Two-input logic circuit. This circuit (called a NAND logic circuit) takes two logical inputs $A$ and $B$. (We draw each of these inputs at two different locations to simplify the diagram.) Note that the PMOS transistors (connecting $V_{DD}$ to $Z$) are in parallel, while the NMOS transistors (connecting $Z$ to ground) are in series. These complementary configurations of NMOS and PMOS transistors guarantee that $Z$ is always shorted to either ground or $V_{DD}$ but not both at the same time, as verified in the 4 cases shown in Table 3.

$A$ $B$ Logic Circuit with Substitutions $Z$ Explanation
$0$ $0$
$1$ $Z$ is shorted to $V_{DD}$ through both PMOS transistors and isolated from ground by both NMOS transistors.
$0$ $1$
$1$ $Z$ is shorted to $V_{DD}$ through the PMOS transistor with input $A$ and isolated from ground by the NMOS transistor with input $A$.
$1$ $0$
$1$ $Z$ is shorted to $V_{DD}$ through the PMOS transistor with input $B$ and isolated from ground by the NMOS transistor with input $B$.
$1$ $1$
$0$ $Z$ is isolated from $V_{DD}$ by both PMOS transistors and shorted to ground through both NMOS transistors.

Figure 4

Fig. 4: Four-input logic circuit. This circuit takes four logical inputs $A$, $B$, $C$ and $D$. Note that the PMOS and NMOS transistor arrangements are complementary. That is, $V_{DD}$ is connected to $Z$ through the parallel combination of two pairs of series PMOS transistors, while $Z$ is connected to ground through the series combination of two pairs of parallel NMOS transistors. One quick way to analyze this logic circuit is to realize that $Z=1$ if ($A$ and $B$ are both $0$) or ($C$ and $D$ are both $0$) by looking at the PMOS transistors. Conversely, observe that $Z=0$ if ($A$ or $B$ are $1$) and ($C$ or $D$ are $1$) by looking at the NMOS transistors. These insights are summarized in Table 4, which is known as the truth table for this logic circuit.

$A$ $B$ $C$ $D$ $Z$
$0$ $0$ $0$ $0$ $1$
$0$ $0$ $0$ $1$ $1$
$0$ $0$ $1$ $0$ $1$
$0$ $0$ $1$ $1$ $1$
$0$ $1$ $0$ $0$ $1$
$0$ $1$ $0$ $1$ $0$
$0$ $1$ $1$ $0$ $0$
$0$ $1$ $1$ $1$ $0$
$1$ $0$ $0$ $0$ $1$
$1$ $0$ $0$ $1$ $0$
$1$ $0$ $1$ $0$ $0$
$1$ $0$ $1$ $1$ $0$
$1$ $1$ $0$ $0$ $1$
$1$ $1$ $0$ $1$ $0$
$1$ $1$ $1$ $0$ $0$
$1$ $1$ $1$ $1$ $0$
Table 4: Truth table for the 4-input logic circuit in Fig. 4.

The logic circuits in Fig. 2, Fig. 3 and Fig. 4 illustrate the key principles of CMOS design: the PMOS transistors sit between $V_{DD}$ and the output; the NMOS transistors sit between the output and ground; and the PMOS and NMOS transistors are laid out in complementary fashion, in which every series combination in the PMOS transistors is matched by a parallel combination in the NMOS transistors, and vice versa. When a logic circuit does not adhere to these design rules, it may be unreliable and sometimes also power-inefficient, as shown by the next two examples.

Figure 5

Fig. 5: Improperly constructed logic circuit with MOSFETs in series. (a) This circuit consists of two PMOS transistors in series and two NMOS transistors in series. These two configurations are not complementary. (b) When $A=0$ and $B=1$, the output $Z$ is isolated from both $V_{DD}$ and ground. The voltage measured at $Z$ could be any value, so $Z$ is said to be floating. In this way, the output of this circuit is unreliable. (Actually, this behavior can be used on purpose to disconnect the output from the circuit, so that it can connect to another circuit, but this kind of three-state logic is strictly speaking no longer binary.)

Figure 6

Fig. 6: Improperly constructed logic circuit with MOSFETs in parallel. (a) This circuit consists of two PMOS transistors in parallel and two NMOS transistors in parallel. These two configurations are not complementary. (b) When $A=0$ and $B=1$, the output $Z$ is shorted to both $V_{DD}$ and ground. The voltage measured at $Z$ is likely to be some value that falls into the undefined range in Fig. 1. Furthermore, $V_{DD}$ is shorted to ground, allowing a large current to flow and a large amount of power to be dissipated. So, this circuit is both unreliable and power-inefficient.

CMOS logic circuits can be combined to create more complex circuits, which in turn can be combined to create even more sophisticated structures. In ECE 120: Introduction to Computing, you will use this process to build memory, arithmetic functions (such as adders) and ultimately microprocessors.

Figure 7

Fig. 7: Cascaded CMOS logic circuit. This circuit is the concatenation of the NAND logic circuit in Fig. 3 and the NOT logic circuit in Fig. 2. We derive the overall truth table by using Table 3 to track inputs $A$ and $B$ to the intermediate output $Y$, and then using Table 2 to track $Y$ to the output $Z$. The circuit is called an AND logic circuit because it turns out that $Z=1$ if and only if $A=1$ and $B=1$.

$A$ $B$ $Y$ $Z$
$0$ $0$ $1$ $0$
$0$ $1$ $1$ $0$
$1$ $0$ $1$ $0$
$1$ $1$ $0$ $1$
Table 5: Truth table for the 2-input AND logic circuit in Fig. 7

In a complex CMOS circuit, each MOSFET is linked at its output to the gate terminals of one or more downstream MOSFETs. In Fig. 7, for example, the 4 MOSFETs that comprise the NAND logic circuit feed into the gate terminals of the 2 MOSFETs that comprise the NOT logic circuit. Since gate terminals behave like capacitors connected to the semiconductor body, we can model each upstream MOSFET's load as a capacitance $C$.

Recall that the energy stored by a capacitor is $0.5CV^2$ J. Thus, each time a MOSFET's output goes from $0$ to $1$ and back to $0$, the load capacitance charges and discharges with $0.5CV_{DD}^2$ J of energy. An additional $0.5CV_{DD}^2$ J is wasted during each cycle due to inefficient charging. (Charging a capacitor efficiently requires the applied voltage to be increased gradually, but this would be too slow for high-performance electronics.) Therefore, a MOSFET consumes a total of $CV_{DD}^2$ J of energy every time its output completes a full cycle. If the MOSFET switches at a rate of $f$ Hz (i.e. cycles per second), then its power consumption is $fCV_{DD}^2$ W.

We now extend this analysis to an entire chip. Suppose the chip contains $n$ MOSFETs but only a proportion $a$ of them are actively switching output at any time on average. Then the average number of switching MOSFETs on the chip is $na$, where the proportion $a$ is known as the activity factor. Finally, if $C$ is the MOSFETs' average load capacitance and $f$ is the cycling frequency of the chip, the power consumption of the chip is:
\begin{align}
P &= nafCV_{DD}^2 \label{LOG-POW}
\end{align}

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