Spring 2018

ECE 110

Course Notes

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A BJT can be wired into a circuit in many different ways. One way to use it as an amplifier or switch is to connect it in the common emitter configuration.

Figure 1

Common emitter circuit
Fig. 1: Common emitter circuit. The emitter of the BJT is wired directly to ground. The input voltage source $V_{\text{in}}$ is connected through resistor $R_1$ to the base. A constant voltage source $V_{CC}$ is connected through resistor $R_2$ to the collector.

In this arrangement, there are two loops, called the input and output loops because they go through $V_{\text{in}}$ and $V_{\text{out}}$, respectively.

Figure 2

Common emitter circuit loops
Fig. 2: Common emitter circuit loops. Applying KVL around the input loop gives: $V_{\text{in}}=I_B R_1 + V_{BE}$. Applying KVL around the output loop gives: $V_{CC}=I_C R_2 + V_{CE}$.

Rearranging these two KVL equations:
\begin{align}
V_{BE} &= V_{\text{in}} - I_B R_1 \label{CEB-EQ1}\\
V_{CE} &= V_{CC} - I_C R_2 \label{CEB-EQ2}
\end{align}
The common emitter circuit is often drawn without complete loops in order to reduce clutter. You should become familiar with both ways of drawing this circuit.

Figure 3

Alternative way to draw the common emitter configuration
Fig. 3: Alternative way to draw the common emitter configuration. This circuit is identical to the one in Fig. 1. Here, $V_{\text{in}}$ is connected to its own ground symbol, but all grounds are implicitly connected to each other, so this is the same as before. Also, the constant voltage source $V_{CC}$ is replaced by a node with fixed voltage $V_{CC}$. Since nothing electrical has changed, the input and output loop KVL equations $\eqref{CEB-EQ1}$ and $\eqref{CEB-EQ2}$ are still true.



In the common emitter configuration, the input port of the BJT is the connection from base to emitter. This portion of an NPN BJT is just like a p-n junction. Consequently, the $I_B\text{-}V_{BE}$ relationship in the common emitter configuration is the same as the I-V characteristic of a diode. Just as for the diode, we model this input I-V characteristic using the offset ideal model except that the threshold voltage for $V_{BE}$ is called $V_{BE,\text{on}}$. The typical value of $V_{BE,\text{on}}$ for a silicon BJT is 0.7 V.

Figure 4

Model for input I-V characteristic
Fig. 4: Model for input I-V characteristic. If $V_{BE} < V_{BE,\text{on}}$, we approximate $I_B=0$. Otherwise, if $I_B > 0$, we approximate $V_{BE}=V_{BE,\text{on}}$.

From this model and equation $\eqref{CEB-EQ1}$, we draw the following conclusions about the input loop of a common emitter circuit:
\begin{align}
&\text{If } V_{\text{in}} < V_{BE,\text{on}} \text{, then } V_{BE} = V_{\text{in}} \text{ and } I_B = 0. \label{CEB-EQ3}\\
&\text{If } V_{\text{in}} > V_{BE,\text{on}} \text{, then } V_{BE} = V_{BE,\text{on}} \text{ and } I_B > 0. \label{CEB-EQ4}
\end{align}


In the common emitter configuration, the output port of the BJT is the connection from collector to emitter. The $I_C\text{-}V_{CE}$ relationship depends on $I_B$. Thus, the output I-V characteristic consists of a set of curves, one for each value of $I_B$.

Figure 5

Output I-V characteristic
Fig. 5: Output I-V characteristic. In the common emitter configuration, all the I-V curves start from $I_C=0$ and $V_{CE}$ equal to some threshold value. For a given value of $I_B$, the curve increases steeply until it reaches a level proportional to $I_B$, at which point it flattens (but not completely).

With this kind of output I-V characteristic, you can analyze BJT circuits graphically using the load line method. But it is more common to use a simpler model of the I-V characteristic to perform circuit analysis.

Figure 6

Model for output I-V characteristic
Fig. 6: Model for output I-V characteristic. In this model, all the I-V curves start from $I_C=0$ and $V_{CE}=V_{CE,\text{sat}}$, called the saturation voltage. If $I_B=0$, the curve is $I_C=0$ for all $V_{CE} \geq V_{CE,\text{sat}}$. If $I_B > 0$, then $I_C=\beta I_B$ for all $V_{CE} > V_{CE,\text{sat}}$. The typical value of $V_{CE,\text{sat}}$ for a silicon BJT is 0.2 V.

From this model, we draw the following conclusions about the output loop of a common emitter circuit:
\begin{align}
&\text{If } I_B = 0 \text{, then } I_C = 0. \label{CEB-EQ5}\\
&\text{If } I_B > 0 \text{ and } V_{CE} > V_{CE,\text{sat}} \text{, then } I_C = \beta I_B. \label{CEB-EQ6}\\
&\text{Otherwise, } V_{CE} = V_{CE,\text{sat}}. \label{CEB-EQ7}
\end{align}


You can use equations $\eqref{CEB-EQ1}$ to $\eqref{CEB-EQ7}$ to analyze a common emitter BJT circuit like the ones in Fig. 1 and Fig. 3. But instead of treating circuit analysis as a math problem, let us develop intuition about these models.

We take the following as given: the input voltage $V_{\text{in}}$; the circuit constants $V_{CC}$, $R_1$ and $R_2$; and the BJT parameters $\beta$, $V_{BE,\text{on}}$ and $V_{CE,\text{sat}}$. We now show how equations $\eqref{CEB-EQ1}$ to $\eqref{CEB-EQ7}$ define three operating modes for the BJT, called OFF, ACTIVE and SATURATED, and derive expressions for $V_{BE}$, $I_B$, $I_C$ and $V_{CE}$ in each mode.

Conditions Mode Behavior: Derivation and Reasons
$\begin{aligned} V_{\text{in}}& < V_{BE,\text{on}}\end{aligned}$ OFF $\begin{aligned} V_{BE}&=V_{\text{in}} & &\text{from BJT input model } \eqref{CEB-EQ3} \\ I_B&=0 & &\text{from BJT input model } \eqref{CEB-EQ3} \\ I_C&=0 & &\text{from BJT output model } \eqref{CEB-EQ5} \\ V_{CE}&=V_{CC} & &\text{from output loop KVL } \eqref{CEB-EQ2} \end{aligned}$
$\begin{aligned} V_{\text{in}}& > V_{BE,\text{on}} \\ V_{CE}& > V_{CE,\text{sat}} \end{aligned}$ ACTIVE $\begin{aligned} V_{BE}&=V_{BE,\text{on}} & &\text{from BJT input model } \eqref{CEB-EQ4} \\ I_B&=\frac{V_{\text{in}}-V_{BE,\text{on}}}{R_1} & &\text{from input loop KVL } \eqref{CEB-EQ1} \\ I_C&=\beta I_B & &\text{from BJT output model } \eqref{CEB-EQ6} \\ V_{CE}&=V_{CC}-I_C R_2 & &\text{from output loop KVL } \eqref{CEB-EQ2} \end{aligned}$
$\begin{aligned} V_{\text{in}}& > V_{BE,\text{on}} \\ V_{CE}&\ngtr V_{CE,\text{sat}} \end{aligned}$ SATURATED $\begin{aligned} V_{CE}&=V_{CE,\text{sat}} & &\text{from BJT output model } \eqref{CEB-EQ7} \\ I_C&=\frac{V_{CC}-V_{CE,\text{sat}}}{R_2} \equiv I_{C,\text{sat}} & &\text{from output loop KVL } \eqref{CEB-EQ2} \\ V_{BE}&=V_{BE,\text{on}} & &\text{from BJT input model } \eqref{CEB-EQ4}\\ I_B&=\frac{V_{\text{in}}-V_{BE,\text{on}}}{R_1} & &\text{from input loop KVL } \eqref{CEB-EQ1} \end{aligned}$
Table 1: BJT operating modes.

Note that $I_{C,\text{sat}}$, which is called the saturation current, is the maximum value of $I_{C}$ among all the modes. In contrast, $V_{CE,\text{sat}}$ is the minimum value of $V_{CE}$. After some practice, you are expected to recall and evaluate the derivation for each mode by looking at a circuit diagram like Fig. 1 or Fig. 3.


The flowchart shown below solves a common emitter circuit problem when the following are given: $V_{\text{in}}$, $V_{CC}$, $R_1$, $R_2$, $\beta$, $V_{BE,\text{on}}$ and $V_{CE,\text{sat}}$. The procedure works by systematically testing whether the BJT is OFF, ACTIVE or SATURATED.

Figure 7

Flowchart for common emitter circuit analysis
Fig. 7: Flowchart for common emitter circuit analysis.

Compare the input voltage $V_{\text{in}}$ with the BJT parameter $V_{BE,\text{on}}$.

If $V_{\text{in}} < V_{BE,\text{on}}$, the BJT is OFF. Then follow the OFF mode derivation in Table 1 to obtain $V_{BE}$, $I_B$, $I_C$ and $V_{CE}$, and you are done!

If $V_{\text{in}} > V_{BE,\text{on}}$, the BJT is not OFF. Continue to the next step.

Assume that the BJT is ACTIVE.

Determine $V_{BE}$, $I_B$, $I_C$ and $V_{CE}$ by following the ACTIVE mode derivation in Table 1.

Compare the value you obtain for $V_{CE}$ with $V_{CE,\text{sat}}$.

If $V_{CE} > V_{CE,\text{sat}}$, your assumption is correct: the BJT is indeed ACTIVE. You are done!

If $V_{CE}\ngtr V_{CE,\text{sat}}$, your assumption is wrong: the BJT is not ACTIVE. Continue to the next step.

The BJT must be SATURATED.

Recalculate $V_{CE}$ and $I_C$ by following the SATURATED mode derivation in Table 1. The values of $V_{BE}$ and $I_B$ are the same as in step 3, so you do not have to recalculate them.


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