Appendix B. x86 Instruction Reference

Table of Contents
B.1 Key to Operand Specifications
B.2 Key to Opcode Descriptions
B.3 Key to Instruction Flags
B.4 General Instructions
B.5 SIMD Instructions (MMX, SSE)
Originally written by Julian Hall and Simon Tantham.

This appendix provides a incomplete list of the machine instructions which NASM will assemble, and a short description of the function of each one. SSE2, 3DNow!, Cyrix MMX, and some undocumented or obsoleted instructions are not included in this list due to space concerns in the lab manual. See the NASM manual for a complete list of all the instructions NASM will assemble.

It is not intended to be exhaustive documentation on the fine details of the instructions' function, such as which exceptions they can trigger: for such documentation, you should go to either Intel's Web site, http://developer.intel.com/design/Pentium4/manuals/ or AMD's Web site, http://www.amd.com/.

Instead, this appendix is intended primarily to provide documentation on the way the instructions may be used within NASM. For example, looking up LOOP will tell you that NASM allows CX or ECX to be specified as an optional second argument to the LOOP instruction, to enforce which of the two possible counter registers should be used if the default is not the one desired.

The instructions are not quite listed in alphabetical order, since groups of instructions with similar functions are lumped together in the same entry. Most of them don't move very far from their alphabetic position because of this.

B.1 Key to Operand Specifications

The instruction descriptions in this appendix specify their operands using the following notation:

Registers

reg8 denotes an 8-bit general purpose register, reg16 denotes a 16-bit general purpose register, and reg32 a 32-bit one. fpureg denotes one of the eight FPU stack registers, mmxreg denotes one of the eight 64-bit MMX registers, and segreg denotes a segment register. In addition, some registers (such as AL, DX or ECX) may be specified explicitly.

Immediate operands

imm denotes a generic immediate operand. imm8, imm16 and imm32 are used when the operand is intended to be a specific size. For some of these instructions, NASM needs an explicit specifier: for example, ADD ESP,16 could be interpreted as either ADD r/m32,imm32 or ADD r/m32,imm8. NASM chooses the former by default, and so you must specify ADD ESP,BYTE 16 for the latter.

Memory references

mem denotes a generic memory reference; mem8, mem16, mem32, mem64 and mem80 are used when the operand needs to be a specific size. Again, a specifier is needed in some cases: DEC [address] is ambiguous and will be rejected by NASM. You must specify DEC BYTE [address], DEC WORD [address] or DEC DWORD [address] instead.

Restricted memory references

One form of the MOV instruction allows a memory address to be specified without allowing the normal range of register combinations and effective address processing. This is denoted by memoffs8, memoffs16 and memoffs32.

Register or memory choices

Many instructions can accept either a register or a memory reference as an operand. r/m8 is a shorthand for reg8/mem8; similarly r/m16 and r/m32. r/m64 is MMX-related, and is a shorthand for mmxreg/mem64.